1. Field of the Invention
The present invention relates to a 4-2 compressor circuit that can calculate the sum of four incoming partial products and a carry input applied thereto and then furnish first and second carries generated during the calculation of the summation, and a voltage holding circuit for use in such a 4-2 compressor circuit.
2. Description of the Prior Art
Referring now to FIG. 15, there is illustrated a schematic circuit diagram showing the structure of a prior art 4-2 compressor circuit as disclosed by Mori et al., "A 10-ns 54.times.54-b Parallel Structured Full Array Multiplier with 0.5-.mu.m CMOS Technology", IEEE J. Solid-State Circuits, Vol. 26, No. 4, pp. 600-605. A plurality of such 4-2 compressor circuits are arranged in the form of an array within a multiplier so that each of the plurality of 4-2 compressor circuits corresponds to each of a plurality of partial products and each of a plurality of bits of a multiplicand. Each 4-2 compressor circuit is used to calculate the sum of partial products.
In FIG. 15, reference numeral 201 denotes a first calculation circuit for implementing the logical exclusive OR operation on two inputs X3 and X4, 202 denotes a second calculation circuit for implementing the logical exclusive OR operation on two inputs X1 and X2, 203 denotes a third calculation circuit for implementing the logical exclusive OR operation on the logical exclusive OR calculated by the first calculation circuit 201 and the logical exclusive OR calculated by the second calculation circuit 202, and 204 denotes a fourth calculation circuit for implementing the logical exclusive OR operation on the logical exclusive OR calculated by the third calculation circuit 203 and a carry input (Carry-in shown in FIG. 15) applied thereto and for furnishing the logical exclusive OR implementation result (Sum shown in FIG. 15) indicating the sum of the five inputs: the carry input and the other four inputs X1 to X4.
In addition, reference numeral 205 denotes a fifth calculation circuit for furnishing an output at logic 1 when the four inputs X1 to X4 are (0, 0, 0, 0), (0, 0, 0, 1), (0, 0, 1, 0), (0, 1, 0, 0), (1, 0, 0, 0), (1, 0, 0, 1), (0, 1, 1, 0), (0, 1, 0, 1), or (1, 0, 1, 0), and for furnishing an output at logic 0 otherwise, 206 denotes a sixth calculation circuit for inverting the logical exclusive OR of the output of the third calculation circuit 203 and the output of the fifth calculation circuit 205, 207 denotes a seventh calculation circuit for furnishing an output at logic 1 when the output of the third calculation circuit 203, the output of the sixth calculation circuit 206, and the carry input applied thereto are (0, 0, 0), (0, 0, 1) or (1, 0, 0), and for furnishing an output at logic 0 when the output of the third calculation circuit 203, the output of the sixth calculation circuit 206, and the carry input applied thereto are (0, 1, 0), (0, 1, 1) or (1, 0, 1), and 208 denotes an eighth calculation circuit for inverting the output of the seventh calculation circuit 207 and for furnishing the inverted output as a second carry (Carry-out1 shown in FIG. 15).
Furthermore, reference numeral 209 denotes a ninth calculation circuit for furnishing an output at logic 1 when the four inputs X1 to X4 are (0, 0, 0, 0), (0, 0, 0, 1), (0, 0, 1, 0), (0, 1, 0, 0), (1, 0, 0, 0), (0, 0, 1, 1), or (1, 1, 0, 0), and for furnishing an output at logic 0 otherwise, and 210 denotes a tenth calculation circuit for inverting the output of the ninth calculation circuit 209 and for furnishing the inverted output as a first carry (Carry-out2 shown in FIG. 15).
Referring next to FIG. 16, there is illustrated a table showing a relationship between the inputs and outputs of the prior art 4-2 compressor circuit as shown in FIG. 15. The first through fourth calculation circuits 201 to 204 can calculate the sum of the four inputs X1 to X4 and the carry input. The fourth calculation circuit 204 can then furnish the summation result. The first through third and fifth through eighth calculation circuits 201 to 203 and 205 to 208 can calculate a second carry from the four inputs X1 to X4 and the carry input. The eighth calculation circuit 208 can then furnish the second carry. The ninth and tenth calculation circuits 209 and 210 can calculate a first carry from the four inputs X1 to X4 and then furnish the first carry. The truth table of FIG. 16 shows a relationship between the four inputs X1 to X4 and the outputs: the summation result Sum, the first carry Carry-out2, and the second carry Carry-out1.
A problem with such a prior art 4-2 compressor circuit that is so constructed as mentioned above is that it has to wait for the determination of the values of the four incoming signals before it starts calculating the sum of the four inputs and the carry input because there are variations in the times when the values of the four incoming signals are determined by a preceding circuit, and this results in making it difficult to improve the computational speed of the prior art 4-2 compressor circuit.
Another problem is that since each of a number of calculation circuits included in one prior art 4-2 compressor circuit includes a number of P-channel transistors and N-channel transistors, a large layout area is needed when integrating those calculation circuits into one chip. So, it is difficult to reduce the layout area of one prior art 4-2 compressor circuit and hence the layout area of a multiplier including a plurality of such prior art 4-2 compressor circuits.